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While loop in VHDL, how do you code it?

4 Answers

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by (1.8k points)

VHDL While Loop

Quick Syntax

while n <= 31 loop
...some statements here...
n := n + 1;
end loop;

Purpose

The while loop is much like its software cousin, it will keep looping until the top statement is no longer true.

In relation to FPGA digital design, the while loop isn't necessarily equipped to be useful for synthesizable code. While some synthesis tools may support partial use of it, I've never seen it used in my entire professional coding career. And I'll never use it there.

However, it is useful in simulation. You can come up with all sorts of possibilities to test your code using while loops. Therefore, I would recommend that you never use it in sythesizable code, but use it freely in simulation code.

Best Practices

1. Keep your while loop usage to simulation only.

2. Be careful with the conditions, don't create an infinite loop.
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by (700 points)

A while loop is a conditional loop for executing code in a repetitive manner. It's most often used in simulation and much less in synthesizable code.

Example:

some_simulation_process : process ( some_input ) is
variable index : integer := 1 ;
begin
loop_label : while i <= 66 loop
output ( index ) <= input ( index + 7 ) after 35 ns;
index := index + 1 ;
end loop ;
end process some_simulation_process ;
0 votes
by (700 points)

while expression loop
sequence_of_statements
end loop;

While an "expression" is true it repeats sequence_of_statements.

function ceilog(x,base:integer) return integer is 
variable s: integer:=1;
variable i: integer:=0;
begin
while (s<x) loop
s:=s*base;
i:=i+1;
end loop;

return i;
end ceilog;

function integer_log2(v : in natural) return integer is
variable log2count : integer := 0;
variable x : integer := v;
begin
while x > 1 loop
log2count := log2count + 1;
x := (x + 1) / 2;
end loop;
return log2count;
end function integer_log2;
0 votes
by (700 points)

A while loop is used when we want to repeat a set of statements while a certain condition remains true. The sytax is pretty simple and given below:

while condition loop
statements;
end loop;

It means that the code represented by statements will run until the condition is false. The Condition can be any expression that can be evaluated to boolean true or false e.g. i<20. The condition is evaluated at the end of each iteration and if it holds true, the iteration is repeated.

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