VHDL While Loop
Quick Syntax
while n <= 31 loop
...some statements here...
n := n + 1;
end loop;
Purpose
The while loop is much like its software cousin, it will keep looping until the top statement is no longer true.
In relation to FPGA digital design, the while loop isn't necessarily equipped to be useful for synthesizable code. While some synthesis tools may support partial use of it, I've never seen it used in my entire professional coding career. And I'll never use it there.
However, it is useful in simulation. You can come up with all sorts of possibilities to test your code using while loops. Therefore, I would recommend that you never use it in sythesizable code, but use it freely in simulation code.
Best Practices
1. Keep your while loop usage to simulation only.
2. Be careful with the conditions, don't create an infinite loop.