# VHDL Convert to Integer?

in VHDL

VHDL best way to convert to integer? Is it to_integer?

by (1.8k points)

## VHDL Convert To Integer

### Quick Syntax

It's recommended that you use the numeric_std library on new designs. Here's how to use the to_integer function:
``````library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;.......signal input : std_logic_vector(15 downto 0);.......-- if input is signed
output <= to_integer(signed(input));-- if input is unsigned
output <= to_integer(unsigned(input));``````
Note that you can also use the conv_integer function from the library std_logic_arith, but this is not recommended on new designs.

### Purpose

VHDL is a very strict typed language. Therefore, it's important that you are careful about which type you are using and which type you are converting to. As mentioned earlier, there are 2 very useful libraries to help with conversions:

1. std_logic_arith - created by Synopsys and commonly used in the older days before ieee created a standard library for this functionality
2. numeric_std - created by ieee and recommended for new designs

You should not use both of these in your designs, since they have overlapping functions, and you may not know which one your tools are using on your design. It's recommended that you go with numeric_std. However, if older designs use std_logic_arith, there's no need to change it.

With that said, using numeric_std, you can easily convert std_logic_vector to integer by first type casting it as signed or unsigned, and then using the to_integer function.

However, keep in mind that a standard integer type in VHDL is 32-bits, and has a range of -2,147,483,648 to +2,147,483,647. So you need to take this into account with the width of your std_logic_vector when converting.

When in doubt, consider looking at the code in the main libraries yourself to see exactly what they are doing. Here's an example of the numeric_std library: https://www.csee.umbc.edu/portal/help/VHDL/numeric_std.vhdl

### Best Practices

1. Use the ieee.numeric_std library for your conversion functions. It also has math functions as well that are common and useful.

2. If older designs use ieee.std_logic_arith, they are fine, leave them alone.

3. Don't use both ieee.numeric_std and ieee.std_logic_arith libraries on the same design, they have conflicting functions.

4. With the library ieee.numeric_std, use the function to_integer to convert a std_logic_vector into an integer. First cast the std_logic_vector as either signed or unsigned, then use to_integer to convert.
by (700 points)

There is no best way.

- to_integer shall be used when the design uses the recommended standard ieee.numeric_std library.
- conv_integer shall be used when the design uses the non-recommended ( for new designs ) ieee.std_logic_arith library.

by (700 points)

Almost yes, but not always. Usually, I use ieee.numeric_std. To convert an unsigned data from std_logic_vector: to_integer(unsigned(data)). For a signed data - to_integer(signed(data)).

``signal in1  : unsigned(3 downto 0);signal in2:   signed(3 downto 0);signal out1 : integer;signal out2: integer;out1 <= to_integer(in1);out2 <= to_integer(in2);``
``````signal in_test   : std_logic_vector(3 downto 0);signal out_1 : integer;signal out_2 : integer;-- assuming in_test is unsigned