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in VHDL by (200 points)

What is the If statement in VHDL, what is the syntax? How do I use it?

4 Answers

0 votes
by (1.8k points)

VHDL If Statement

Quick Syntax

PROC_IF : process (clk)
begin
if rising_edge(clk) then
output <= input;
end if;
end process;

Purpose

The if statement is one of the most commonly used things in VHDL. It's most basic use is for clocked processes. This is also known as "registering" a signal. The output signals are updated on the next edge of the clock cycle.

You can also build even more complex logic with layers of if statements.

The if statement also has other options like else if and else that can be used. That's been covered in another question thread, so check that one out if you want to learn more about these.

Examples

Here's the proper way to do a clock enable:
PROC_IF : process (clk)
begin
if clock_en = '1' then
if rising_edge(clk) then
output <= input;
end if;
end if;
end process;
Notice how we keep the clock_en signal as a separate if statement to make it easy for the synthesis tool to figure out that it's really a clock enable.

Here's how to do an asynchronous reset:
PROC_IF : process (clk)
begin
if reset = '1' then
output <= '0';
elsif rising_edge(clk) then
output <= input;
end if;
end process;
Here's how to do a synchronous reset, which is recommended on Xilinx parts for the past several years to help routing:
PROC_IF : process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
output <= '0';
else
output <= input;
end if;
end if;
end process;

Best Practices

1. If statements are very common, so master them.

2. You can have multiple layers of if statements.

3. If your if statement gets too big, consider using a case statement instead for cleaner code.
0 votes
by (700 points)

The 'if' statement is a conditional statement that's used for decision making. Every 'if' statement MUST be terminated by an 'end if' statement. In VHDL 'if' will usually synthesize to a MUX.

Example :

signal counter : integer ;
signal output : std_logic ;

if_example : process ( counter ) is
begin
if counter > 50 then
output <= '1' ;
elsif counter < 50 then
output <= '0' ;
end if ;
end process if_example ;
0 votes
by (700 points)

This is a conditional statement that depending on the value of the condition expressions, selects for execution of one of the enclosed sequence of statements. Syntax:

if expression then
sequence_of_statements
(elsif expression then
sequence_of_statements)*
(else
sequence_of_statements)?
end if;

I typically use it when I need to define a simple conditional choice, when using of a combinational logic is either harder for coding or worse for a readability: not a big MUX for example, or some simple conditional data processing with reports. For a wide choice of inputs or for a FSM the case statement is better.

Example:

if cmd_arr(tRD+2).activate ='1' and cmd_arr(tRD+2).fifo_read = '0' then
if time_s.cs_counter(1) = '0' then
std.textio.write(l,string'("AES "));
else
std.textio.write(l,string'("MUX "));
end if;

--WRITELINE(MyFile,l); std.textio.write(l,string'("read memory chip: "));
write(l,hex_string(cmd_arr(tRD+2).cs)); write(l,' ');
std.textio.write(l,string'(" bank: "));
write(l,hex_string(cmd_arr(tRD+2).bank)); write(l,' ');
std.textio.write(l,string'(" addr: "));
write(l,hex_string(cmd_arr(tRD+2).addr and addr_mask)); write(l,' ');
write(l,hex_string(data_i)); write(l,' ');

elsif cmd_arr(tRD+3).activate ='1' and cmd_arr(tRD+3).fifo_read = '0' then
write(l,hex_string(data_i)); write(l,' ');
WRITELINE(MyFile,l);

elsif cmd_arr(CMD2WRDATA+1).activate ='1' and cmd_arr(CMD2WRDATA+1).fifo_read = '0' then
std.textio.write(l,string'(" bank: "));
write(l,hex_string(cmd_arr(CMD2WRDATA+1).bank)); write(l,' ');
std.textio.write(l,string'("write memory "));
write(l,hex_string(cmd_arr(CMD2WRDATA+1).addr and addr_mask)); write(l,' ');
write(l,hex_string(data_s)); write(l,' ');

elsif cmd_arr(CMD2WRDATA+2).activate ='1' and cmd_arr(CMD2WRDATA+2).fifo_read = '0' then
write(l,hex_string(data_s));
WRITELINE(MyFile,l);
end if;
0 votes
by (700 points)

Like in all other programming languages, the if statement in VHDL is a conditional statement. The code inside an If Statement only executes if certain conditions are true. The syntax is given below.

if condition then
inside_statements
end if;

The above-given syntax is for using the simplest form of an if statement. 'if', 'then' and 'end if' are VHDL keywords. This snippet of code means that the lines of code inside the if statement represented by inside_statements, executes only when the 'condition' is true.

The condition can be any expression like 'var <10', meaning that if variable var is less than 10, then execute inside_statement.

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