VHDL If Statement
Quick Syntax
PROC_IF : process (clk)
begin
if rising_edge(clk) then
output <= input;
end if;
end process;
Purpose
The if statement is one of the most commonly used things in VHDL. It's most basic use is for clocked processes. This is also known as "registering" a signal. The output signals are updated on the next edge of the clock cycle.
You can also build even more complex logic with layers of if statements.
The if statement also has other options like else if and else that can be used. That's been covered in another question thread, so check that one out if you want to learn more about these.
Examples
Here's the proper way to do a clock enable:
PROC_IF : process (clk)
begin
if clock_en = '1' then
if rising_edge(clk) then
output <= input;
end if;
end if;
end process;
Notice how we keep the clock_en signal as a separate if statement to make it easy for the synthesis tool to figure out that it's really a clock enable.
Here's how to do an asynchronous reset:
PROC_IF : process (clk)
begin
if reset = '1' then
output <= '0';
elsif rising_edge(clk) then
output <= input;
end if;
end process;
Here's how to do a synchronous reset, which is recommended on Xilinx parts for the past several years to help routing:
PROC_IF : process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
output <= '0';
else
output <= input;
end if;
end if;
end process;
Best Practices
1. If statements are very common, so master them.
2. You can have multiple layers of if statements.
3. If your if statement gets too big, consider using a case statement instead for cleaner code.