VHDL Examples?

Question

What are some good VHDL examples for newbies?

Answer 1

Examples:

-- and gate :
z <= x and y ;

-- or gate :
z <= x or y ;

-- xor gate :
z <= x xor y ;

-- not gate :
z <= not x ;

-- single line conditional statement :
output <= '1' when some_signal = 500 else '0' ;

-- very simple clock division :
clock_division_by_2 : process ( INPUT_CLOCK ) is
begin
  if rising_edge ( INPUT_CLOCK ) then
    div_2_clock <= not div_2_clock ;
  end if ;
end process clock_division_by_2 ;

-- shift right register :
shifter_register_right : process ( INPUT_CLOCK ) is
begin
  if rising_edge ( INPUT_CLOCK ) then
    shift_register <= input & shift_register ( 7 downto 1 )  ;
  end if ;
end process shifter_register_right ;

-- shift left register :
shifter_register_left : process ( INPUT_CLOCK ) is
begin
  if rising_edge ( INPUT_CLOCK ) then
    shift_register <= shift_register ( 6 downto 0 ) & input ;
  end if ;
end process shifter_register_right ;

-- register with an asynchronous reset :
asynchronous_reset : process ( INPUT_CLOCK , INPUT_RESET ) is
begin
  if INPUT_RESET = '1' then
    some_signal <= ( others => '0' ) ;
  elsif rising_edge ( INPUT_CLOCK ) then
    some_signal <= some_other_signal ;
  end if ;
end process shifter_register_right ;

-- register with a synchronous reset :
synchronous_reset : process ( INPUT_CLOCK ) is
begin
  if rising_edge ( INPUT_CLOCK ) then
    if INPUT_RESET = '1' then
      some_signal <= ( others => '0' ) ;
    else
      some_signal <= some_other_signal ;
    end if ;
  end if ;
end process synchronous_reset ;

-- register with both an asynchronous and synchronous reset :
synchronous_reset : process ( INPUT_CLOCK , INPUT_ARESET ) is
begin
  if INPUT_ARESET = '1' then
    some_signal <= ( others => '0' ) ;
  elsifif rising_edge ( INPUT_CLOCK ) then
    if INPUT_SRESET = '1' then
      some_signal <= ( others => '0' ) ;
    else
      some_signal <= some_other_signal ;
    end if ;
  end if ;
end process synchronous_reset ;

-- 2 stage synchronizer :
synchronizer : process ( INPUT_CLOCK ) is
begin
  if rising_edge ( INPUT_CLOCK ) then
    registered_1_input <= input ;
    registered_2_input <= registered_1_input ;
  end if ;
end process synchronizer ;

-- un-pipelined adder :
slow_adder : process ( INPUT_CLOCK ) is
begin
  if rising_edge ( INPUT_CLOCK ) then
    result <= a + b + c;
  end if ;
end process slow_adder ;

-- pipelined adder :
fast_adder : process ( INPUT_CLOCK ) is
begin
  if rising_edge ( INPUT_CLOCK ) then
    a_plus_b <= a + b ;
    result <= a_plus_b + c;
  end if ;
end process fast_adder ;

More good ( but more complex ) examples for newbies are :

De-bouncing circuit
Binary to one hot encoder
One hot to binary encoder
Binary to Grey converter
UART circuit
SPI circuit
Barrel shifter
Asynchronous FIFO
Synchronous FIFO

Answer 2

I think newbies should first try to code a clock, reset, and a counter. For example:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
generic (
  D_WIDTH : integer := 8
  );
port (
  reset_n_i : in std_logic;
  clk_i : in std_logic;
  q_o : out std_logic_vector(D_WIDTH-1 downto 0)

  );
end entity;

architecture rtl of counter is

signal cnt : unsigned(D_WIDTH-1 downto 0) := (others => '0');

begin

process (clk_i)
  begin
    if rising_edge(clk_i) then
      cnt <= cnt + 1;
      if reset_n_i = '0' then
        cnt <= (others => '0');
      end if;
    end if;
end process;

q_o <= std_logic_vector(cnt);

end;

And:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb
end entity;

architecture behav of tb is

component counter is
generic (
  D_WIDTH : integer := 8);
port (
  reset_n_i : in std_logic;
  clk_i : in std_logic;
  q_o : out std_logic_vector(D_WIDTH-1 downto 0));
end component;

signal clk : std_logic := '0';
signal reset_n : std_logic_vector(3 downto 0) := x"0";
constant D_WIDTH : integer := 8;
signal dut_result : std_logic_vector(D_WIDTH-1 downto 0);

begin

process
begin
  clk <= '0';
  wait for 5 ns;
  clk <= '1';
  wait for 5 ns;
end process;

process (clk)
begin
  if rising_edge(clk) then
    reset_n <= reset_n(2 downto 0) & '1';
    report "counter output = " & integer'image(to_integer(unsigned(dut_result)));
  end if;
end process;

dut: counter
generic map (
  D_WIDTH => D_WIDTH)
port map (
  reset_n_i => reset_n(3),
  clk_i => clk,
  q_o => dut_result);

end

Answer 3

For beginners, it is easier to start by implementing basic logic gates using VHDL. This helps them get familiar with the language and learn how to do define signals, architectures etc. For example, to implement a simple AND gate, we need two inputs and one output. First of all, hardware input/output ports are defined in an entity. Entity is a VHDL keyword and its use is explained below:

entity newbie_code is
port (
  in1    : in  std_logic;
  in2    : in  std_logic;
  and_output : out std_logic
  );
end newbie_code;

Here, newbie_code is the name of the entity that we are defining which contains two inputs: in1 and in2, and one output and_output. The inputs and outputs are of std_logic type. As you know in all programming languages, variables must have a type, here the type is std_logic, which means it can have either a value of 0 or 1 (for now). The keywords in and out define whether the ports are input or output. Now that the entity is defined, we can define the architecture :

architecture rtl of newbie_code is

signal and_gate : std_logic;

begin
  and_gate <= in1 and in2;
  and_output <= and_gate;
end rtl;

A signal is declared inside the architecture of std_logic type. This signal, and_gate, is assigned the value of the result we get when in1 is anded with in2. '<=' is the assignment operator. Finally, and_gate is assigned to our output. This concludes the code of an AND gate implementation. The only thing left is to remember to include libraries at the top of the code that contains the definitions of functions used in the code. For the above code we must include these lines at the top:

library ieee;
use ieee.std_logic_1164.all;

Some other great examples to look at are implementation of MUX, adder, XOR gate, flip flops etc.