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in VHDL by (240 points)

What is a VHDL variable and how do I use it?

3 Answers

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by (1.8k points)

VHDL Variable

Quick Syntax

PROC_VAR: process (input1,input2)
variable my_var : std_logic := '0';
my_var := '0'; -- reset every time process runs
if input1 = '1' then
my_var <= '0';
my_var <= '1';
end if;

output1 <= my_var;

if input2 = '1' then
my_var <= '1';
my_var <= '0';
end if;

output2 <= my_var;

end process;


The purpose of variables in VHDL is in cases where you need to drive outputs of a process by something that will change throughout the process, and you need to capture each of those changes.

Variables are like a local memory storage ability. Whereas with signals in processes, you get the last valid option in the process as it goes from top to bottom.

Some people like using variables, many do not. In my professional experience, I rarely come across variables.

Personally, I never use them. Why? Because you can do the same functionality with multiple signals, and most people don't know how to use variables correctly. Therefore, it's a bit risky to use them in code that you want to be easily maintainable by others.

I usually see lots of newbies use them incorrectly. Perhaps because they think it's close to a software language variable for which they are comfortable with. However, this is hardware description, not software.

My recommendation would be to use them rarely, and only in cases where you can't get the same functionality without using them. However, I would challenge that you can always do without them.

Best Practices

1. Many people don't know how to use variables correctly, so if you use them, chances are someone else coming behind you will probably break your code.

2. If you do use variables, make sure you understand how to use them correctly.

3. Some people like variables, many do not. They are just another option in the language. They come with a risk if you are working with others.

4. If you need multiple outputs throughout a process based on the same variable, you can do the same functionality with multiple signals instead and forgo using variables.
0 votes
by (500 points)

VHDL variables are elements similar to signals with the exception that they can be used only inside a process, function or procedure. Variables are also local to the process in which they have been declared. I.E: a variable declared in one process can't be used in another process.

Assigning a value to variable must be done using the ':=' blocking assignment operator and therefore will happen immediately. When designing synthesizable logic - usage of variables is generally limited to describing combinatorial logic.

0 votes
by (500 points)

This is a variable as in other programming languages. The area in a memory to store data. The variable assignment performs immediently in the place and in the moment when a processing flow reaches it. A variable assignment doesn't generate any events that place into a time loop. Sometimes it is very usefull to store intermediate results in variables instead of assigning complicated expressions to signals in complicated statements so it helps to simplify an algorithms implementation.

All HDL models describe circuits that contain combinational logic and registration stages (flip-flops). All signal assignments in synchronous processes produce registers after some combinational asynchronous logic.

We can use variables to simplify that combinational asynchronous logic implementation and moreover to control a value of its "logic level" (this affects performance). A "logic level" in simple terms - is a number of logic elements on a path between flip-flops.


process (all)
v := s;
v := some_processing(p1, p2, p3, p4);
s_next <= v;
end process;

process (clk)
if rising_edge(clk) then
s <= s_next;
end if;
end process;
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