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What is a VHDL testbench generator and how do I use them?

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A test bench generator is software that can receive a design entity and automatically create a VHDL test bench around it. The generator will provide a template for driving stimulus to the signals and free the designer from some of the coding effort. Such generators are used for building test environments for simulating and verifying your code.

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My testbench generator is my mind :) Allthough I know about such generators. But I don't know about a generator that can work with user types - the ones I know support only VHDL standard types. Regardless, these generators may be usefull to rapid check of a designed rtl: compilation, elaboration etc.

Also, it may be usefull to rapidly construct a skeleton, a core body of test where you can place your test code. Sometimes, it can generate a good test with randomization. Some of these generators are waveform-based (i.e. at the beginning needs to define a waveform from which it generates stimuli, https://www.itdev.co.uk/content/vhdl-testbench-generator-tool if I'm not mistaken) others use a VHDL entity declaration as a base to generate a general testbench code (http://www.edautils.com/VHDLTBGen.html, https://www.doulos.com/knowhow/perl/testbench_creation/). I think the second ones are better.

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