VHDL Port Map
Quick Syntax
Here's how you declare the ports at the top of your design source file:
entity my_module is
port(
clk : in std_logic;
reset : in std_logic;
input_en : in std_logic;
output : out std_logic);
end my_module;
And here is how you instantiate your module in another source file like your top level. In this example we instantiate it twice:
MODULE1 : entity work.my_module
port map (
clk => clk,
reset => reset,
input_en => module1_input_en,
output => module1_output);
MODULE2 : entity work.my_module
port map (
clk => clk,
reset => reset,
input_en => module2_input_en,
output => module2_output);
Purpose
The purpose of ports and a port map is to give you the ability to create a standalone entity that is a design source, and then you have the ability with a port map to instantiate that entity any number of times that you want in any part of your design. It also allows you to connect the ports to signals in the higher level file where you are instantiating it.
Think of it as naming the pins of your part.
Note that in my examples I am using the better method of referencing the entity in its compiled library, such that you don't need to do a component declaration. This is recommended and used by the pros. Newer versions of VHDL after 87 allow this, which reduces repetitive code that can be problematic to maintain.
The "MODULE1 : entity work.my_module" is how you do this method, assuming that it was compiled in the library work.
Best Practices
1. Use entity references by library and skip component declarations.
2. Pay careful attention to your last port pin as far as commas or semicolons, and the need for a close parenthesis and semicolon.
3. In your instantiations, you should always drive inputs on the port map, but you can leave outputs open by putting the word open as the signal connection.