VHDL Concatenate
Quick Syntax
Symbol: &
-- concatenate two signals
output <= input1 & input2;
-- concatenate two 0's on the right side with a signal
output <= input1 & "00";
-- concatenate two 0's on the left side with a signal
output <= "00" & input2;
Purpose
Concatenation in VHDL is combining multiple items into one item. The requirement is that the output must match the same bit width as the total bit width of the items that you are concatenating.
It is used a lot in VHDL designs. You will commonly see it in write and read registers that support bus interfaces like PCI, VME, etc. These buses are often 32-bit or 64-bit and each register can control multiple signals that might be 1-bit or multiple bits wide.
So in order to read a full 32-bit register that represents multiple signals, the regsiter read must concatenate all of these signals together to form the full 32-bit register.
Concatenation is most commonly used for std_logic and std_logic_vector types.
Best Practices
1. The concatenation symbol is: &
2. Concatenation is very common and used everywhere in VHDL.
3. Make sure that your output bit width matches the total of the inputs that you are concatenating.
4. Pay attention to clock domains of your inputs. Don't make the tools guess which clock domain the output should abide by on timing constraints. Do proper clock domain crossing first before you concatenate items from different clock domains.