Here's the most common VHDL types that you will come across:
constant CONSTANT_REAL : real := 2.0;
signal input_boolean : boolean;
signal input_sl : std_logic;
signal input_slv : std_logic_vector(15 downto 0);
signal count_integer : integer;
signal count_natural : natural;
signal count_positive : positive;
VHDL is a strictly typed language. That means, that you have to be very precise in dealing with type and how those types interact. While it seems "harder" to learn, it also means that you remove the majority of your bugs with a successful compile at synthesis.
Of course, you will encounter other bugs due to wrong assumptions, flawed logic, bad coding practices, clocking, timing, etc. But at least it won't be because your signals aren't compatible with each other.
You get quite a few predefined data types right out of the box. Every design file typically adds the IEEE library std_logic_1164, which also gives you types std_logic and std_logic_vector.
Keep in mind that there are other types as well, which are less commonly used, such as: bit, bit_vector, char, etc. You can read up on how these are a little different if you want. Just keep in mind that they are far less common.
With the types given above, you can do around 99.9% of designs.
As far as range of these types, check out the list below:
real: 128-bits, range = -1.0E38 to +1.0E38
boolean: True or False
std_logic: single bit '1' or '0', including other states
std_logic_vector(N downto 0): multiple N+1 bits at '1' or '0', including other states
integer: 32-bits, range = -2,147,483,647 to +2,147,483,647
natural: 31-bits, range = 0 to +2,147,483,647
positive: 31-bits, range = 1 to +2,147,483,647
By using the ieee.numeric_std library, you can also get access to the signed and unsigned type, as well as do math arithmetic operations.
If you want to define your own type, you can do it like this:
-- define state machine states and enumerate them
type my_states is (idle, start, done);
signal sm_state : my_states;
-- define array of std_logic_vector
type type_array_slv is array (0 to 31) of std_logic_vector(7 downto 0);
signal output_bus : type_array_slv;
1. Try to stick to the predefined types and also std_logic and std_logic_vector that you get with the ieee.std_logic_1164 library. There are many other libraries that offer different types. However, watch out for library conflicts if you use too many.
2. You can define your own custom type, which is pretty common. You can use this to define arrays of predefined types easily. It's also a great way to define states in a state machine.