FIFO stands for first in, first out and is a great way to implement a buffer in VHDL. There are two types of FIFO's:
1. Synchronous - common clock on input and output
2. Asynchronous - different clocks on the input and output
A great use of a synchronous FIFO is as buffer storage. For example, video line buffers, interface message buffers, etc. Any place where you find a limit on getting data across an interface you'll probably need a buffer and a FIFO will usually do the trick.
A great use of an asynchronous FIFO is proper clock domain crossing for data. By allowing one clock on the input side and a different clock on the output side, it offers a great way to transfer data across the clock domain boundary without having metastability issues. It can act as buffer storage too at the same time.
FIFOs can also be used to change data widths from one side to another.
Believe it or not, FIFO's can get a bit complicated to implement. In theory, they are pretty simple, but you need to be able to handle a lot of low level synchronization. There is usually some logic wrapped around some memory primitives (like BRAM).
It's recommended that you use the FPGA manufacturer's IP generator to create core files that you can instantiate in your design. With a few simple mouse clicks, those generators will get you a reliable core design that handles all of the low level issues for you.
For example, both Xilinx and Altera offer some great options in their FIFO generators. It can also generate the files that you need to simulate your design as well, making things go quickly and smoothly for the implementation.
Both of these tools have great documentation on how to use the IP generator and what the different options do. So go grab a copy of the documentation for the specific IP generator you have available and spend a little time reading up on the FIFO sections. Everything that you need to know is usually laid out in those guides for you.
1. FIFOs are very handy and common.
2. Use the FPGA manufacturer's FIFO generator to create core files that you can instantiate in your design. Don't waste time trying to roll your own FIFO from scratch.
3. Pay attention to clock domain crossings and use an asynchronous FIFO for data on clock crossings to avoid metastability problems.
4. Use the IP generated files for your simulation to make sure that you are interacting with the FIFO correctly in your design.