Convert To Unsigned in VHDL
Quick Syntax
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
-- convert from natural integer to unsigned
output1 <= to_unsigned(input_natural, output1'length);
-- convert from std_logic_vector to unsigned (either one works the same)
output2 <= to_unsigned(input_slv);
-- which does the same as this in the library:
output2 <= unsigned(input_slv);
Purpose
Because VHDL is a strict type language, often times you will need to go back and forth between types in a design. Luckily, there are some great functions out there already built into common libraries.
It's best to use the ieee.numeric_std on new designs, which gives you lots of ways to convert between types, as well as math functions.
Nand Land has a great write up on the different conversions of types here:
https://www.nandland.com/vhdl/tips/tip-convert-numeric-std-logic-vector-to-integer.htmlBest Practices
1. It's recommended to use the ieee.numeric_std library on new designs. There are many convenient conversion functions in that library, including to_unsigned which will convert a natural integer and a std_logic_vector to unsigned.
2. For older designs that use the ieee.std_logic_arith library there's no need to change anything. The conversion function in this library is conv_unsigned.