VHDL Component Declaration
Here's how you do a component declaration:
clk : in std_logic;
reset : in std_logic;
input_en : in std_logic;
output : out std_logic);
However, since VHDL-93, you no longer have to do component declarations, and in fact, it's recommended that you don't in most situations (read why below). Let me show you the recommended way that the pro's use next.
Assuming you compiled your entity in the library work, here is how you directly instantiate your entity in another source file like your top level:
MODULE1 : entity work.my_module
port map (
clk => clk,
reset => reset,
input_en => module1_input_en,
output => module1_output);
Note that with this method, component declarations are not needed.
The purpose of the component declraration in VHDL-87 was to let the tools know what the port pins are. However, that information is already known in the design source file as the entity. Therefore, in VHDL-93, they started allowing you to directly instantiate an entity, bypassing the need for component declarations altogether.
Please note that older text books and internet articles have not been updated with the VHDL language changes that have taken place over the past 30+ years since VHDL-87. As noted, in the old days, you had to do component declarations and port maps so that the tools could find all of your source files. That means you had the same ports in 3 places: design source file, component declaration, and component instantiation.
However, with VHDL-93, the language woke up to the crys of many engineers and realized that having the same kind of code in three places causes all sorts of headaches and a maintenance nightmare.
So they came up with a better way where you can directly instantiate the specific entity without having to use component declarations. That way you only need the source file ports, and then wherever it's being instantiated, you simply reference it with something like this: MODULE1 : entity work.my_module, where work is the library that it was compiled into. This is the method I'm using in this answer post.
Even after all of these years, you still see people doing the old way which is crazy. The biggest sign of someone looking like a newbie in VHDL is if they do component declarations. It went out of fashion long ago with the pros. It's not just a fashionable thing, any port map changes requires another change if component declarations are used, which is cumbersome.
Why use component declarations? If you have mixed language designs, like VHDL and Verilog, then you will need to do component declarations for the Verilog source files in your design. That way the tools know what the pins are and can marry up the port maps with the Verilog modules.
1. Only use component declarations for mixed language designs, i.e. to declare a Verilog module. Otherwise, directly instantiate an entity by referring to it's compile library and name.
2. Make sure you get those pesky commas and semicolons right and close parenthesis, unless you enjoy many compile failures.