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How do you shift left in VHDL? What is the best method?

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Shift Left in VHDL

Quick Syntax

-- shift left 1-bit
output(15 downto 0) <= input(14 downto 0) & '0';

-- shift left 4-bits output(15 downto 0) <= input(11 downto 0) & "0000";

Purpose

Shifting left happens a lot in digital design. While there are functions out there, like shift_left from the ieee.numeric_std library, many people may not know exactly what the library does and will have to either guess or go look it up if they come across your code.

That's why I prefer do it manually, since it's about the same lines of code, and it's clear what is happening. Usually, functions are only helpful if they save multiple lines of code.

The risk is that functions are contained in libraries that can change, conflict, or be removed. Plus people may not know how they work which creates wasted time in either bugs from misuse or having to go look something up for code maintenance.

Best Practices

1. Ideally, you can easily shift left with regular code, which is ideal, clear, and easy to maintain.

2. If you must use a function, use the shift_left in the library ieee.numeric_std.
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by (500 points)

There are 3 methods to shift bits left in VHDL:

1. Shift Left Logical operator :

signal output : std_logic_vector ( 7 downto 0 ) ;
output <= output sll 3 ; -- Will simply pad the 3 LSB's with "000".
2. Shift Left Arithmetic operator :
signal output : signed ( 7 downto 0 ) ;
output <= output sla 3 ; -- Will pad the 3 LSB's with respect to the sign bit.
3. Concatenation :
signal input : std_logic ;   
signal output : std_logic_vector ( 7 downto 0 ) ;
output <= output ( 6 downto 0 ) & input ; -- Will pad the LSB with the value of input.
0 votes
by (500 points)

I use the concatenation operator usually. For example:

shiftreg : std_logic_vector(D_WIDTH-1 downto 0);

shiftreg <= shiftreg(shiftreg'left-1-shift_offset downto 0) & data_i;

or

shiftreg <= shiftreg(shiftreg'left) & shiftreg(shiftreg'left-2-shift_offset downto 0) & data_i; (if it is an arithmetical left shift)

There is one more way without using either library functions or operators:

  for i in 0 to shift_offset loop
shiftreg <= shiftreg(shiftreg'left-1 downto 0) & '0';
end loop;
or for arithmetic shift left:
  for i in 0 to shift_offset loop
shiftreg(shiftreg'left-1 downto 0) <= shiftreg(shiftreg'left-2 downto 0) & '0';
end loop;
There also is the library function shift_left() and operators sll and sla. Firstly, there are problems with these operators, so it is better to use the shift_left() function. You can read about these problems there: http://jdebp.eu./FGA/bit-shifts-in-vhdl.html

If you will pass a signed data to shift_left - it will be an arithmetic left shift. If you will pass an unsigned data to shift_left - it wil be a logical left shift.
-- there shiftreg : unsigned(D_WIDTH-1 downto 0) or shiftreg : signed(D_WIDTH-1 downto 0)
shiftreg <= shift_left(shiftreg, shift_offset);

If the shift_offset is an object of an array type, You need to convert it to integer (it would be better if to natural).
-- there shiftreg : unsigned(D_WIDTH-1 downto 0) or shiftreg : signed(D_WIDTH-1 downto 0)
shiftreg <= shift_left(shiftreg, to_integer(unsigned(shift_offset)));

If You want use sll and/or sla You must do it much carefully and with full understanding what do You really do. Sll may do an arithmetical shift for signed inputs, both sll and srl can take a negative shift, and do something with it in operators overloading. But all these may affect negatively to a synthesis. So it si better to use it in the same way as the shift_left() function.

To use these functions You need to use a corresponding package. numeric_std - for unsigned/signed which are inherited from std_logic_vector, numeric_bit - for unsigned/signed which areinherited from bit_vector.

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