D Flip Flop in VHDL?

Question

What is a D flip flop and how do I code it in VHDL?

Answer 1

A D Flip Flop or "DFF" is a basic 1 bit - volatile synchronous storage element. It's the synchronous equivalent of a D Latch. At the most basic form it has 2 inputs ( clock , d ) and one output ( q ). Its operation is very simple - what it does is drive the output 'q' with the value 'd' when a clock edge arrives ( the edge can be either rising or falling ). A DFF is the basic building block of all modern FPGAs and is essential in any synchronous design.

Example :

signal d , q : std_logic ;

dff :process ( clock ) is
begin
  if rising_edge ( clock ) then
    q <= d ;
  end if ;
end process dff ;

Answer 2

The D flip-flop actually is just a little different from the clocked SR flip-flop. The D input is connected to the S input and the inverted D input connects to the R input. The D input is sampled by a clock pulse. When 1, the flip-flop switches to the set state (Q -> 1). When 0 the flip-flop switches to the reset state (Q -> 0). In simple terms the D flip-flop just samples the d input by clock edge.

library ieee;
use ieee.std_logic_1164.all;

entity d_flipflop is
  port (
    clk : in std_logic;
    d : in std_logic;
    q : out std_logic;
    qn : out std_logic
  );
end entity;

architecture rtl of d_flipflop is
  signal state : std_logic;
begin
  process (clk)
  begin
    if rising_edge(clk) then
      state <= d;
    end if;
  end process;

  q <= state;
  qn <= not state;
end;