Interested In VHDL Training? Click Here

0 votes
in VHDL by (200 points)

What is the symbol for not equal in VHDL?

3 Answers

0 votes
by (1.8k points)

VHDL Not Equal

Symbol: /=

Quick Syntax

if input1 /= input2 then
output <= '0';
output <= '1';
end if;


Obviously, the not equal symbol is used for comparing two things and returns True if they are different.

In my experience of coding, I rarely come across not equal. Typically, most peope write their code for checking if things are equal, and using an else for all cases when they are not equal. It seems that most people's minds work that way.

While there are some rare cases where you must use a not equal check, one could argue that you could easily use an equal check instead with slightly different code.

For example, in our situation above, it could easily of been written this way instead which is much clearer:
if input1 = input2 then
output <= '1';
output <= '0';
end if;
0 votes
by (500 points)

The VHDL symbol for not equal is '/='

Example :

signals comparator_result : std_logic ;
signal x , y : signed ( 10 downo 0 ) ;

comparator_result <= '0' when x /= y else '1' ;
0 votes
by (500 points)

This simbol is /=. This operator is used to define a relation between two VHDL objects in the conditional expression of if-else statements, conditional signal assignment, generate statements, etc. The best description of it's behavior is the VHDL standard.

The equality and inequality operators (= and /=) are defined for all types other than file types and protected types. The inequality operator returns the value FALSE if the two operands are equal and returns the value TRUE otherwise. Cases in which the inequality operator returns TRUE follow from the description of when objects are equal in VHDL.

"Two scalar values of the same type are equal if and only if the values are the same. Two composite values of the same type are equal if and only if for each element of the left operand there is a matching element of the right operand and vice versa, and the values of matching elements are equal, as given by the predefined equality operator for the element type. In particular, two null arrays of the same type are always equal. Two values of an access type are equal if and only if they both designate the same object or they both are equal to the null value for the access type.

For two record values, matching elements are those that have the same element identifier. For two onedimensional array values, matching elements are those (if any) whose index values match in the following sense: the left bounds of the index ranges are defined to match; if two elements match, the elements immediately to their right are also defined to match. For two multidimensional array values, matching elements are those whose indices match in successive positions."

So if any two objects that can be compared (i.e. have the same base type) does not satisfy the relations are described above they are not equal.

Want to improve your VHDL skills?

Click Here - Sign Up For VHDL Training

© 2022 by Hardware Coder. User contributions are licensed under cc by-sa 4.0 with attribution required. Attribution means a link to the question, answer, user, etc on this site.

This site is owned and operated by Hardware Coder in McKinney, Texas.

Send Us A Message
About Us

By using this site, you agree to the following:

Privacy Policy
Terms and Conditions
DMCA Policy
Earnings Disclaimer
Legal Disclaimer