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in VHDL by (240 points)

What is a VHDL signal? How do I do a signal declaration, initialize a signal and do a signal assignment?

3 Answers

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by (1.8k points)

VHDL Signals

Quick Syntax

-- signal declaration
signal my_sl      : std_logic;
signal my_slv : std_logic_vector(7 downto 0);
signal my_integer : integer;

......

-- and you can initialize signals like this: signal my_sl : std_logic := '0';
signal my_slv : std_logic_vector(7 downto 0) := "00001000";
signal my_integer : integer range -4 to 4;

......

-- signal assignment my_sl <= '0';
my_slv <= "11111111"; -- or you can write it in hex: x"00" my_integer <= 3;

-- signal assignment from other inputs or signals my_sl <= input_sl;
my_slv <= input_slv;
my_integer <= other_integer;

Purpose

The purpose of signals is for connecting pins of entities, components, etc. You also use signals to write logic. Signals can be many different types, but make sure that when they interact with each other, they are compatible since VHDL is strictly typed.

Prior to VHDL-2008, you could not read pins that were outputs. The common solution was to use a signal internally, and then drive the output pin with that signal so that you can also read that signal as needed.

VHDL-2008 allows you to directly read output pins, so you don't have to use an intermediate signal. However, not all tools are fully compatible with VHDL-2008, even now in 2020.

Personally, I continue to use the prior method of internal signals if they need to be read. That way, my code can work on VHDL all the way back including older designs and tool chains.

Best Practices

1. Signals are a foundational way of connecting things in VHDL.

2. You can initialize signals with a := when you declare it. However, while it usually works in most simulators, you will need to consult with your synthesis tool documentation to see how it's implemented in hardware.
0 votes
by (500 points)

A VHDL signal is an element that holds a value. A good way to think of it is as an electrical wire. A signal must have a type. It's possible to assign a default value for a signal ( which is usually done in simulation ).

Example :

signal green_led : std_logic ;

green_led <= '1' ; -- The signal green_led is driven high.
0 votes
by (500 points)

Signals are the primary objects describing a digital hardware. In some sense signals are equivalent to wires. Some might say that signals represent communication channels among concurrent statements of a system's specification.

This is valid but if you will imagine that each process that includes control of multiple signals as multiple processes that controls only a single signal per process. In simple and coding-based terms, signals are such variables that have a design-wide scope, history of changes and programable sequence of future changes using events and the time loop.

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