Resize In VHDL
Quick Syntax
There's a function in the ieee.numeric_std library called "resize", which is used like this:
new_size <= resize(unsigned(old_size_std_logic_vector), 16);
new_size <= resize(signed(old_size_std_logic_vector), 16);
However, it may not do exactly what you want based on most significant or least significant bit behavior (read more below). I always prefer to do things manually here so that you know exactly what you are getting, especially since it doesn't take many lines of code:
-- go from 8 to 16 bits, pad most significant bits with 0's
new_size <= x"00" & old_size;
-- go from 8 to 16 bits, pad least significant bits with 0's
new_size <= old_size & x"00";
-- go from 16 to 8 bits, use most significant bits
new_size <= old_size(15 downto 8);
-- go from 16 to 8 bits, use least significant bits
new_size <= old_size(7 downto 0);
The above examples were for std_logic_vector types.
Purpose
The need to resize things comes up often in VHDL. As mentioned earlier, you do have a function avaiable in the numeric_std library. However, it may not do exactly what you want.
From the documentation on the numeric_std library, here's the description of the resize function:
"-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped."
Notice that the input must be signed or unsigned, so you will need to cast a std_logic_vector as those first. You can do this by signed(my_signal) or unsigned(my_signal).
Best Practices
1. I rarely see pros use the resize function. It doesn't give you much savings on code lines, and most people don't know exactly if it pads left or pads right, so they have to waste time to look it up when they come across it in code.
2. I prefer to manually resize std_logic_vector types so that I can quickly and easily see exactly what is happening.