VHDL std_logic_vector?

Question

What is a std_logic_vector in VHDL? How do you use it?

Answer 1

A std_logic_vector is a standard VHDL type. It's essentially a vector of std_logics - the same way that bit_vector is a vector bits. It's intention is to represent the electrical values of elements.

std_vector ( and therefore also std_logic_vector ) can accept a total of 9 values :

'U': Uninitialized. This signal hasn't been set yet.
'X': Unknown. Impossible to determine this value/result.
'0': Logic 0.
'1': Logic 1.
'Z': High Impedance.
'W': Weak signal, can't tell if it should be 0 or 1.
'L': Weak signal that should probably go to 0.
'H': Weak signal that should probably go to 1.
'-': Don't care.

Note :
Not all of the above values will be supported in synthesis. Some are intended for simulation only.

Answer 2

This is an array which elements are of the type std_logic.

type std_logic_vector is array (integer range <>) of std_logic;

Basicaly this type is an unconstrained array type. So you need to use a subtype indication based on this type to declare objects. In simple terms you need to define a range.

signal stdlv0 : std_logic_vector(d_width-1 downto 0);
variable stdlv1 : std_logic_vector(stdlv0'range);
signal stdlv2 : std_logic_vector(0 to stdlv0'length+3);