Rising edge in VHDL?

Question

How do I use a rising edge in VHDL?

Answer 1

VHDL Rising Edge

Quick Syntax

If you are asking about a clock's rising edge, it's this:

if rising_edge(clk) then
  output <= input;
end if;

If you are asking about a discrete signal's rising edge, then the easiest way is to register the signal which causes a 1 clock delay, then AND the original signal with a not version of the delayed signal. Here's an example:

PROC_RISING_EDGE_DETECT : process (clk,reset)
begin

  if rising_edge(clk) then

    if (reset = '1') then
      input_1q <= '0';
    else
      -- delay input by 1 clock
      input_1q <= input;

      -- detect rising edge
      rising_edge_detect <= input and (not input_1q);
    end if;

  end if;
end process;

Purpose

Clocks:

In digital design, a lot of what we do has to do with signal edges.

Synchronous designs use a clock to drive logic. Therefore, a clock edge is a special event where things happen. There is two ways to use a rising edge of a clock:

1. (clk'event and clk='1')
2. rising_edge(clk)

There is some debate online of which one is "better". I've seen both in my professional career. The general consensus favors using rising_edge(clk) since it seems to handle the different transitions allowed on a std_logic signal, which is what your clock typically will be. That's what I use.

Signals:

You will often need to know when edges of discrete signals occur. Luckily, it's pretty easy to do this with logic in your design. Keep in mind that you cannot use either of the clock options above on discrete signals. The reasons why are beyond the scope of my answer here.

Best Practices

1. Use rising_edge(clk) for your clocks.

2. Use logic to detect rising edges of your other signals. The AND of the original signal and it's delayed not version can be either clocked or outside the process depending on your needs (if you don't want an extra clock delay on the detect). For higher frequency, consider making the detect clocked to help your routing and timing performance.

Answer 2

There are 2 ways to do it. One involves the "rising_edge" operator and second uses ' event.

Examples:

using_rising_egde : process ( clock ) is
begin
  if rising_edge ( clock ) then
    -- do something
  end if ;
end process using_rising_egde ;

using_event : process ( clock ) is
begin
  if ( clock ' event and clock = '1' ) then
    -- do something
  end if ;
end process using_event ;

Answer 3

Two ways:

clk'event and clk = '1'
the function rising_edge - rising_edge(clk)

When you work with std_logic it would be much better to use a function rising_edge. This is it's body:

FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '1') AND
(To_X01(s'LAST_VALUE) = '0'));
END;

This function looks hard determine the behavior of rising edge in meaning of transition from 0 to 1. But if you use clk'event and clk = '1' it may be X -> 1 etc.