VHDL assert?

Question

What is assert in VHDL and how do I use it?

Answer 1

In VHDL - "assert" is a statement that's used for printing messages onto a console of a VHDL simulator.
The statement evaluates a boolean condition ( a condition whose outcome may be either true or false ) and asserts a message when the condition IS NOT met.

Example :

assert_example : process ( clock ) is
begin
  if rising_edge ( clock ) then
    if some_counter < maximum_counter_value then
      some_counter <= some_counter + 1 ;
    else
      assert false report "some_counter overflow" severity error ;
    end if ;
  end if ;
end process assert_example ;

Answer 2

This is a statement that checks that a specified condition is true and reports with a given severity if it is not. This statement is very usefull to check invariants. The kind of formal verification that is included in a designed system's specification. Asserts may be used to check a data transfer protocol, an implementation of a data processing algorithm, or a complicated FSM.

Syntax :assert condition report string severity severity_level;

Examples:

assert SIZE<=2**ADDR_WIDTH
  report "SIZE must be less or equal than 2^ADDR_WIDTH"
  severity failure;

assert MODE="DONTCARE" or MODE="WR_FIRST" or MODE="RD_FIRST" or MODE="NOCHANGE"
  report "Unrecognized MODE value (DONTCARE, WR_FIRST, RD_FIRST or NOCHANGE expected)"
  severity failure;

assert st(j).state_counter = "00" & unsigned(adr_mask(adr_mask'left - 1 downto 1))
  report ("Scratchpad size error. state_counter = " & hex_string(std_logic_vector(st(j).state_counter)) & "Scratchpad done. adr_mask     = " & hex_string(std_logic_vector(adr_mask))) 
  severity error;