Interested In VHDL Training? Click Here

0 votes
in VHDL by (200 points)

VHDL integrated development environments? What do beginners and pros use?

2 Answers

0 votes
by (500 points)

A VHDL IDE is an "Integrated Design Environment" that can be used to fulfill the major steps ( perhaps excluding simulation ) in the VHDL design process. Such as:

1. Parsing the VHDL code.
2. Synthesis of the code to real logic.
3. Placing the logic blocks of the synthesized code of the target device.
4. Routing between the placed logic blocks.
5. Generating a programming file ( in case of FPGA design ) for the target device ).

Some side features of modern IDEs are :

1. Inbuilt text editors.
2. GUIs that allow instantiations and connections between logic blocks.
3. IP catalogs that feature a rich assortment of pre-designed of logic blocks.
4. RTL viewers that allow viewing logic at the hierarchical level.
5. Version control.
6. Pin assignment for FPGA devices.

The choice of IDE isn't differentiated between "beginners" and "pros". Today, the usage of VHDL is limited mainly to FPGA designs. So the choice of IDE has much to do with the FPGA vendor then anything else.

Example :

Quartus - Used exclusively on Intel FPGAs.
Vivado - Used exclusively on Xilinx FPGAs.
Diamond - Used exclusively on Lattice FPGAs.
ISP Lever - Used exclusively on Lattice FPGAs.
Libero - Used exclusively on Microsemi / Actel FPGAs.

0 votes
by (500 points)

A VHDL IDE is almost the same as an IDE of any other language. In general IDE includes:

* text editor
* compiler and/or Interpreter
* build tools
* debugger

Here's what I consider makes for a good IDE:
* text editor
* compiler
* simulation kernel as a build tool (in a sense of binding compiled objects) and part of a debugger (it "runs" a model and gives you an ability to check it and debug it)
* waveforms/scope/waves visualization tools as an another part of debugger

I mostly use Modelsim. I work with it through command line using makefiles. But in dependence of either customer/employer or project details I somtimes use other tools. It may be Active-HDL (one of my customers works only with it and they check both my designs and verification tests out in this software).

I prefer Modelsim over Active-HDL because I use SystemVerilog and DPI for verification that are weakly supported in Active-HDL. But for beginners, it would be much easier to start with Active-HDL (it also includes a testbench generator).

Our verifiers use VCS, so sometimes I need to work with it. This is a good and powerfull tool but I don't see any difference in performance for almost all projects. And sometimes I use simulation tools that are included in FPGA design tools - such the Vivado simulator. This is very comfortable when designing for a Xilinx FPGA and when there's no need for any thorough tests (this is my opinion).

Want to improve your VHDL skills?

Click Here - Sign Up For VHDL Training

© 2022 by Hardware Coder. User contributions are licensed under cc by-sa 4.0 with attribution required. Attribution means a link to the question, answer, user, etc on this site.

This site is owned and operated by Hardware Coder in McKinney, Texas.

Send Us A Message
About Us

By using this site, you agree to the following:

Privacy Policy
Terms and Conditions
DMCA Policy
Earnings Disclaimer
Legal Disclaimer

...