JK Flip Flop in VHDL?

Question

What is a JK Flip Flop and how do I code it in VHDL?

Answer 1

A JK Flip Flop or "JKFF is a 1 bit - volatile synchronous storage element. It's the synchronous equivalent of a JK Latch. At the most basic form it has 3 inputs ( clock , j , k ) and one output ( q ).

When both j and k are '0' the output q maintains the old value at the sensitive clock edge.
When j = '0' k = '1' the output q becomes '0' at the sensitive clock edge.
When j = '1' k = '0' the output q becomes '1' at the sensitive clock edge.
When both j and k are '1' the output q flips at the sensitive clock edge.

Example :

signal j , k , q : std_logic ;

jkff : process ( clock ) is
begin
  if rising_edge( clock ) then
    if j = '0' and k = '1' then
      q <= '0';
    elsif j = '1' and k = '0' then
      q <= '1' ;
    elsif j = '1' and k = '1' then
      q <= not q ;
    end if ;
  end if ;
end process jkff ;

Answer 2

This is an improved SR flip-flop with clock synchronisation. J = 0 and K = 0 - keep the current state, memory no change, J = 1 - Set (Q -> 1), K = 1 - Reset (Q -> 0), J = 1 and K = 1 - Toggle (Q -> not Q)

Example:

library ieee;
use ieee.std_logic_1164.all;

entity jk_flipflop is
  port (
    clk : in std_logic;
    j : in std_logic;
    k : in std_logic;
    q : out std_logic;
    qn : out std_logic
  );
end entity;

architecture rtl of jk_flipflop is
  signal state : std_logic;
begin
  process (clk)
  begin
    if rising_edge(clk) then
      if j = '1' and k = '1' then
        state <= not state;
      elsif j = '1' then
        state <= '1';
      elsif k = '1' then
        state <= '0';
      end if;
    end if;
  end process;

  q <= state;
  qn <= not state;
end;

In general it is sufficient not to define the case of j = '0' and k = '0'. But you can do this if you want to determine a behavior for others values of std_logic (for example if j and/or k are 'X').

architecture rtl of jk_flipflop is
  signal state : std_logic;
begin
  process (clk)
  begin
    if rising_edge(clk) then
      if j = '1' and k = '1' then
        state <= not state;
      elsif j = '1' then
        state <= '1';
      elsif k = '1' then
        state <= '0';
      elsif j = '0' and k = '0' then
        state <= state;
      else
        report "J and/or K aren't of valid values (0 or 1)";
      end if;
    end if;
  end process;

  q <= state;
  qn <= not state;
end;