Interested In VHDL Training? Click Here

0 votes
in VHDL by (200 points)

What are some VHDL basics? Where do I learn?

2 Answers

0 votes
by (500 points)

Important VHDL basic are :

1. Understanding the concept of being a "Strongly Typed" language.
2. What is an entity and a component.
3. Behavior of objects under different types of assignments ( blocking , non-blocking ).
4. What are processes.
5. What are sensitivity lists and why they are important.
6. Different ways of component instantiations.
7. How to write generic code.
8. What is a buffer.
9. What's a "std_logic" and how is it different from a "bit".
10.What's structural description.
11.What's behavioral description.
12. What are the most common data types.
13. When std_logic_vectors should be used vs when unsigned ( or signed ) vectors should be used.
14. What is a Finite State Machine, when is it used and what are the common ways to code one.
15. What's the difference between synthesizable and un-synthesizable VHDL code.
16. Functions and their usage.
17. What are the basics of writing high performance code.

A good first book is "VHDL Primer" by B.Hasker. A good second book is "The Designer's Guide to VHDL" by Petter Ashenden. The internet and forums such as hardwarecoder, stackoverflow, and edaboard are great sources of help.

0 votes
by (500 points)

This question is interesting. 10 years ago I could answer on it without any doubt. But now I start to think is there anything that I can throw out without losing any really useful functionality.

The first thing that you must learn is the core idea of time loop, delta cycles, events, events merging. The last two is tied with signal assignments. This helps you to avoid a lot of dummies bugs. Particular attention should be paid to the influence of delta cycles on synchronous processes. For example, if your process will work by a rising edge of a signal that is clock replicated through several signal assignments it will fail a base principle of such proceses - it will not be simulated as a trigger (OK on synthesis but with wrong behavior in simulation). It may sample a data at the nearest delta cycle instead of the next rising edge of clock.

Before you will start to learn how to code using VHDL you need to learn the basics of circuit design (adders, mux/demux, multipliers, RAM, ROM) , logic, binary mathematic (integer signed/unsigned, two's complement, fixed point, floating point, etc). Without these you won't understand what to do when you code something on VHDL. The next important thing - are types and it's base attributes: length, high, low, left, right, image, range.

Then, understanding of operators from the VHDL standard. Then base VHDL object assignment statements, processes, entities, architectures, components declarations and its instantiation, other statements (if-else, case). You need to learn how to define a memory. Also packages: standard, numeric_bit, std_logic_1164, numeric_std, textio. Assertions and reports, process sensitivity lists, transport and inertial delays, 'wait for' statements.

Then you will need to learn about the timing in the IC's design - setup, hold, metastability and how to deal with it. Gaining new knowledge about VHDL and a hardware design you should then try it in practice. The best way is to find an intern job after you can code and test a simple VHDL design (for example a synchronous FIFO, bus interface such as Avalon-MM/ST or APB, SPI interface or something like this).

I learned HDL and hardware design during my study in college and during work. It's a long learning curve for everyone.

Want to improve your VHDL skills?

Click Here - Sign Up For VHDL Training

© 2022 by Hardware Coder. User contributions are licensed under cc by-sa 4.0 with attribution required. Attribution means a link to the question, answer, user, etc on this site.

This site is owned and operated by Hardware Coder in McKinney, Texas.

Send Us A Message
About Us

By using this site, you agree to the following:

Privacy Policy
Terms and Conditions
DMCA Policy
Earnings Disclaimer
Legal Disclaimer

...