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How do you specify a VHDL integer range?

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VHDL Integer Range

Quick Syntax

signal my_integer : integer;
VHDL assumes that my_integer is 32-bits and can be anything from -2,147,483,647 to +2,147,483,647.
signal my_integer : integer range -5 to 255;
VHDL will limit the range of my_integer from -5 to 255 and will only assign the number of bits required.


Integers are a default type in VHDL. Here's a run down of Integer and it's subtypes: Natural and Positive.

Integer: 32-bits, range = -2,147,483,647 to +2,147,483,647
Natural: 31-bits, range = 0 to +2,147,483,647
Positive: 31-bits, range = 1 to +2,147,483,647

You can restrict the range of these types with the range add on, but you need to keep the original limits in mind when doing so (don't try to make a natural or a positive go past their original lower boundary):
signal my_integer : integer range -16 to 16;
signal my_natural : natural range 0 to 16;
signal my_positive : positive range 1 to 16;
Limiting the range of these types is a great idea when using generics or for ports to protect instantiations from driving the design out of it's expected behavior.

Synthesis tools may or may not have the ability to trim out un-used bits from a 32-bit integers depending on the design. It's generally good practice to limit the range of known signals to help the tools optimize the design properly.

Don't forget that you can set the initial value of the integer like this:
signal my_integer : integer range -16 to 16 := 2;
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by (260 points)

VHDL has seen its rise when the predominant computer architecture was of 32 bits. Although the standard doesn't explicitly specify this - almost all FPGA design software defines the range of an integer as -2,147,483,647 to +2,147,483,647.

This is the default. So if one writes :

signal x : integer ; -- x supports values from -2,147,483,647 to +2,147,483,647.

There is however a way to limit the range of x inside the boundaries of the default.

Example :

signal date_of_month : integer range 1 to 31 ; -- If we'll try to drive the signal with a value not between 1 to 31 we'll get a compilation error.

date_of_month <= 46 ; -- This line will show as erroneous.

0 votes
by (260 points)

Integer type objects in VHDL can have a user-defined range. The range is specified to save FPGA resources. The value of the integer variable/object will lie between the boundary values of the range defined. The boundary values should also be of integer type and locally static. Locally static expressions are those that can be evaluated at compile time.

Boundary values can also be negative and the range can be ascending or descending. Below is an example of integer type signals with their range specified:

signal sig_1 : integer range -9 to 0;
signal sig_2 : integer range 0 to 10;

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