VHDL Integer Range
signal my_integer : integer;
VHDL assumes that my_integer is 32-bits and can be anything from -2,147,483,647 to +2,147,483,647.
signal my_integer : integer range -5 to 255;
VHDL will limit the range of my_integer from -5 to 255 and will only assign the number of bits required.
Integers are a default type in VHDL. Here's a run down of Integer and it's subtypes: Natural and Positive.
Integer: 32-bits, range = -2,147,483,647 to +2,147,483,647
Natural: 31-bits, range = 0 to +2,147,483,647
Positive: 31-bits, range = 1 to +2,147,483,647
You can restrict the range of these types with the range add on, but you need to keep the original limits in mind when doing so (don't try to make a natural or a positive go past their original lower boundary):
signal my_integer : integer range -16 to 16;
signal my_natural : natural range 0 to 16;
signal my_positive : positive range 1 to 16;
Limiting the range of these types is a great idea when using generics or for ports to protect instantiations from driving the design out of it's expected behavior.
Synthesis tools may or may not have the ability to trim out un-used bits from a 32-bit integers depending on the design. It's generally good practice to limit the range of known signals to help the tools optimize the design properly.
Don't forget that you can set the initial value of the integer like this:
signal my_integer : integer range -16 to 16 := 2;