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Best way to convert VHDL to Verilog?

2 Answers

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by (260 points)

One way is to use the VHDL code simply as reference and re-write it line by line in Verilog. Many of the statements in VHDL have direct equivalents in Verilog. This method can be VERY time consuming but gives a lot of manual control during the process.

Another way is to use a VHDL to Verilog converter. This is a software tool that receives a VHDL file and automatically converts the contents to Verilog syntax while trying to maintain bit-exact and cycle-exact functionally.

Example :

VHDL2VERILOG HDL Converter

Note: With big projects - the necessity of conversion should be evaluated as modern design tools usually allow mixed language design input.

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by (260 points)

One way to do it is to use the tool vhd2vl. But this is not an ideal method and the developer will have to do some manual conversions. This will not support the conversion of arrays, packages, and records.

Furthermore, entity instantiation is also not supported. Nevertheless, these failures can be easily fixed by manual conversion. This tool can be downloaded from http://doolittle.icarus.com/~larry/vhd2vl/.

There are other VHDL to Verilog translators available out there like VHDL2Verilog. More details about this tool can be found at http://www.syncad.com/verilog_vhdl_translator.htm

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