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in VHDL by (240 points)

How do you use for generate statements in VHDL?

3 Answers

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by (1.8k points)

VHDL For Generate

Quick Syntax

-- add 2 to an array of integers
GEN_EXAMPLE1: for n in 0 to 7 generate
output(n) <= input(n) + 2;
end generate;

-- instantiate an entity 16 times GEN_EXAMPLE2: for n in 0 to 15 generate
GEN2_INST: entity work.my_entity
port map (
clk => clk,
reset => reset,
input => input(n),
output => output(n));
end generate;


The purpose of for generate statements is to give you the ability to replace many lines of code with much fewer when you have to do multiples of something. It's very convenient for simple things or even instantiating multiple instances of the same entity.

In the above examples, you can see where having the same lines of code to do something 8 times or 16 times would be cumbersome and much harder to maintain for when there are changes. Imagine if you need to do something 100's of times?

By using for generate, you can do something as many times as you want. I often use natural generics and constants to determine the upper bound of the for generate instead of hard wiring in a number there. It gives you a lot of flexibility for making modular code.

Best Practices

1. Use for generate statements when you have to do the same code multiple times to save lines of code and make it easy to maintain.

2. Combine for generate statements with either generics or constants of type natural, which makes it easy to change the number of iterations in the for loop.
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by (300 points)

The VHDL "generate" statement is an important tool for writing generic code in a conditional or repetitive manner. There are 2 types of generate statements that VHDL supports: "if - generate" and "for - generate".

1. "if - generate" is somewhat similar to "ifdef" in C. It's used for conditional generation of code based on an evaluation of a boolean condition.

Example :

  signal alarm : std_logic ;
signal temperature : integer ;
-- The following code will be generated ONLY if "ALARM_REQUIRED" is equal to '1'.
-- "ALARM_REQUIRED" must be a compile time static object like a generic or constant. It can't be a dynamic value such as a signal of input port.
  generate_alarm : if ALARM_REQUIRED = '1' -- ALARM_REQUIRED is can be an entity generic or constant.
alarm <= '1' when temperature > 100 else '0' ;
end generate ;
2. "for - generate" is a statement that allows repetitive generation of code. It helps making the code more generic and compact.

Example :
  type array_of_100_unsigned is array 0 to 99 of unsigned ( 7 downto 0 ) ;
signal x , y , result : array_of_100_unsigned ;

generate_100_adders : for index in 0 to 99 -- The following compact code will generate 100 adders. generate

single_adder : adder

port map
input_a => x ( index ) ,
input_b => y ( index ) ,

output_c => result ( index )
) ;

end generate ;
0 votes
by (300 points)

With generate statements we can implement a conditional or iterative portion of the code. When there is a need of using multiple components with the same specifications, it becomes cumbersome to write the code again and again.

Generate statements can be used to specify multiple identical components by using the specifications of one component. Identical components are created by simply using the generate statement. A generate statement can either have a for scheme or an if scheme. Generation of routine structures where values are similar, a for generation scheme is used.

When there is the need for a specified condition to be met for generating any particular structure, an if generating scheme is used. The general syntax of the generate statement is given below:

label : for parameter in range generate
[ { declarations }
begin ]
{ concurrent_statements }
end generate [ label ] ;

label : if condition generate
[ { declarations }
begin ]
{ concurrent_statements }
end generate [ label ] ;

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