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What is a VHDL entity?

2 Answers

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by (300 points)

An entity is an important concept in VHDL that specifies the interfaces that a "design unit" ( a logic block ) has to the external world. As an analogy to the every day world - one can think of an entity as a full description of all the "doors" that lead to and from a house. It does NOT describe the house's contents though. A "design unit" unit is an entity + architecture pair.

Example :

-- The following entity has 3 input "doors" and one output "door".

entity some_entity is

input_x : in std_logic ;
input_y : in std_logic ;
input_z : in std_logic ;

output_a : out std_logic
) ;

end entity some_entity ;
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by (300 points)

In VHDL, the interface between a design and its external environment is described as an entity. The design is also referred to as a design entity.

While an entity describes the interface between a design entity and its environment of operation, an architecture describes the inner workings of the operation. Therefore, an architecture needs to be assigned to an entity. An entity can be assigned to multiple architectures but each architecture can be assigned to only one entity.

Entity declaration contains three main parts: entity name, generic parameters, and ports. Static information like bus width etc are provided by the generic parameters and ports specify the communication channels.

If any statements are used in entity declaration, care must be taken that they are passive i.e. they do not change any signal. The syntax for entity declaration is given below:

entity entity_name is
generic (generic_list);
port (port_list);]
end entity entity_name;

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