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in VHDL by (240 points)

What is a xor gate and how do I implement it in VHDL?

3 Answers

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by (1.8k points)


Quick Syntax

c <= a xor b;


A XOR gate is also known as an exclusive OR.

Think of it as a simple OR, where if either inputs are a 1, the output is a 1. Except, when both inputs are 1's, the output is a 0. See the truth table below:

A In | B In | C Out
0 0 0
0 1 1
1 0 1
1 1 0

There are situations where you want this logical behavior, and it's easy enough to implement in code. A common use is when you want to detect either a rising or a falling edge on a signal.


Here's how to use a XOR to detect either a rising or falling edge on a signal.
PROC_EDGE_DETECT : process (clk,reset)

if rising_edge(clk) then

if (reset = '1') then
input_1q <= '0';

-- delay input by 1 clock input_1q <= input;

-- detect either edge edge_detect <= input_1q xor input;

end if;

end if;
end process;
If you need the edge_detect above to be aligned with input_1q, you can move the edge_detect <= input_1q xor input; line outside of the process and make it concurrent.

Best Practices

1. Make sure both inputs are either asynchronous or are both on the same clock domain before the XOR gate. Otherwise, you might give your tools some trouble with timing.
0 votes
by (260 points)

In VHDL - "xor" is a predefined native operator. It can be used in a straightforward way.

Example :

signal x,y : std_logic ;
signal x_not_equal_y : std_logic ;

x_not_equal_y <= x xor y ;
0 votes
by (300 points)

Implementation of exclusive-OR or XOR gate is very simple as VHDL contains a key for achieving this. For example, if x and y are inputs and z is the output, the code for implementing a xor in VHDL is:

z <= x xor y;

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