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How do I do division or dividers in VHDL?

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The VHDL language has a predefined division operation '/'. Although its fully supported in simulation - its synthesis support is limited. '/' will usually work in synthesis only when the dividend is constant or the divisor is a power of 2. It can be good for sizing constants during compile time.

Example :

constant vector_width : integer := result = x / y ; -- x and y are entity generics that may change between compilations.

signal vector : std_logic_vector ( vector_width - 1 downto 0 ) ;

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Division is a complex operation because it requires implementation of a complex logic circuit. Hence, it is better to try to avoid it whenever possible and to only use it in special circumstances. If division by 2 is required then the method is pretty straight forward: just shift the binary number to the right.

Like in the case of decimals, when they are divided by their base i.e. 10, the number is shifted to the right. 120 divided by 10 is 12 i.e. 120 sifted to right. The same happens in case of binary numbers when they are divided by their base i.e. 2.

Dividing by powers of two can also be accomplished by shifting. The next case is when we need to divide by a constant. For other scenarios, FPGA vendors provide IPs that can be used for implementing division. Division can also be achieved through CORDIC (Coordinate Rotation Digital Computer).

These approaches are not suitable if we have an area problem. Furthermore, many clock cycles are required for these approaches. However, if the divisor is less than 10/12 bits, mapping values in ROM/LUT (Lookup Table) can be done. Using LUT architecture might be a better approach depending on the requirements.

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