VHDL Sensitivity List
Quick Syntax
PROC_EXAMPLE : process (Hello, I'm the sensitivity list!)
begin
...code statements
end process;
If you notice in the code above, the sensitivity list is saying hello. :)
Purpose
Here's a fun fact that many may not know. The sensitivity list is just to let your simulator know which signals it should watch for changes. Your synthesis tool doesn't change its implementation based on it since it pays attention to your logic instead. However, it probably will take note and issue warnings that it found things missing from your sensitivity list.
Why should you be cautious with your sensitivity list? Because if you don't you'll end up with a simulation that doesn't match hardware, which means you'll end up with bugs when you go on to hardware. It's a terrible idea to be sloppy with the sensitivity list.
You should put all the signals in your sensitivity list that drive events in your code. For example, clocks, resets, and input signals. If your resets are synchronous (clocked), then you can leave them off of your sensitivity list since every time the clock changes, your simulation tool will check everything again.
However, I prefer to put resets in any way just in case someone in the future makes the reset asynchronous and forgets to update the sensitivity list.
Examples
PROC_EXAMPLE : process (clk, reset, input_en)
begin
if rising_edge(clk) then
if reset = '1' then
output_en <= '0';
else
output_en <= input_en;
end if;
end if;
end process;
Best Practices
1. Be a good coder and always include all signals that do something in the process in its sensitivity list.