VHDL Greater Than and Less Than
Quick Syntax
Greater Than Symbol: >
if input1 > input2 than
output <= '1';
else
output <= '0';
end if;
Greater Than or Equal To Symbol: >=
if input1 >= input2 than
output <= '1';
else
output <= '0';
end if;
Less Than Symbol: <
if input1 < input2 than
output <= '1';
else
output <= '0';
end if;
Less Than or Equal To Symbol: <=
if input1 <= input2 than
output <= '1';
else
output <= '0';
end if;
Purpose
Comparison operators like greater than and less than are commonly used in VHDL. The syntax is very basic and pretty easy to get the hang of, simply check out the examples above.
Keep in mind that you have to include a library, where the ieee.numeric_std is recommended on new designs. In order to use these operators, the items that you are comparing must be signed, unsigned, or integer. You can't compare a raw std_logic_vector without casting it as signed or unsigned first.
Here's how you would compare two std_logic_vectors:
if unsigned(input1) <= unsigned(input2) than
output <= '1';
else
output <= '0';
end if;