# VHDL Signed?

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in VHDL

How to use signed in VHDL?

## 2 Answers

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by (260 points)

In VHDL "signed" is a type of vector element that's intended for signed arithmetic operations ( such as comparing to numeric values , adding , subtracting , multiplying , etc... ) Negative numbers are represented using 2's complement. Although arithmetic operations can sometimes be performed on the std_logic_vector type - this is strongly discouraged.

Example 1 :

``signal celcius_temperature : unsigned ( 15 downto 0 ) ;signal water_freeze_alarm : std_logic ;water_freeze_alarm <= '1' celcius_temperature < 0 else '0' ;``
Example 2 :
``````signal number_1 : signed ( 7 downto 0 ) ;   -- Can accept both possitive and negative number ( 2's complement )
signal number_2 : signed ( 7 downto 0 ) ;   -- Can accept both possitive and negative number ( 2's complement )
signal number_3 : signed ( 15 downto 0 ) ;  -- Can accept both possitive and negative number ( 2's complement )
number_3 <= number_1 * number_2 ;``````
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by (300 points)

A signal in VHDL can be defined as either signed or unsigned. An unsigned signal is positive only, but if a signal is defined as signed it can be either positive or negative. Internally, FPGA uses 2's complement to represent negative numbers.

For example, a signed 3-bit signal '011' is interpreted as '3' and '101' is interpreted as '-3'. It is important to note here that if the 3-bit signal was defined as unsigned the '101' would have been interpreted as '5'. This representation of signals is important for performing arithmetic operations.

To use this functionality, numeric_std package must be used which is part of the ieee library. The syntax is as follows:

signal <name> : signed(<N-bits> downto 0) := <initial_value>;