In VHDL "signed" is a type of vector element that's intended for signed arithmetic operations ( such as comparing to numeric values , adding , subtracting , multiplying , etc... ) Negative numbers are represented using 2's complement. Although arithmetic operations can sometimes be performed on the std_logic_vector type - this is strongly discouraged.

Example 1 :

`signal celcius_temperature : unsigned ( 15 downto 0 ) ;`

signal water_freeze_alarm : std_logic ;

water_freeze_alarm <= '1' celcius_temperature < 0 else '0' ;

Example 2 :

```
signal number_1 : signed ( 7 downto 0 ) ; -- Can accept both possitive and negative number ( 2's complement )
signal number_2 : signed ( 7 downto 0 ) ; -- Can accept both possitive and negative number ( 2's complement )
signal number_3 : signed ( 15 downto 0 ) ; -- Can accept both possitive and negative number ( 2's complement )
```

number_3 <= number_1 * number_2 ;