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in Verilog by (240 points)

What are testbenches in Verilog and what is an example?

2 Answers

0 votes
by (260 points)

A testbench is a common name to a simulation environment for testing a logic unit ( or units ). It works on the principle of driving known input values to an existing logic block and observing the values of the outputs. A testbench is an essential part of the design & verification cycle.

Example :

// "tb_counter" is itself a module that encapsulates another module that it's intended to test which is named : "counter"

module tb_counter ;

reg clk ;
wire [3:0] count ;

// "counter" is a module described in another file.

counter connect_counter
(
.clk ( clk ) , // input
.count ( count ) // output
) ;

initial
begin
clk = 0;
end

always
#2 clk = ! clk ;

endmodule
0 votes
by (260 points)

Testbenches are Verilog code that provides a set of stimuli that are portable across different simulators. It must be either a simple set of stimuli (clock, reset, some simple inputs behavior) or a strong well defined test with randomization, logging, protocol control, checks etc.

In general a good testbench must be based on a module's specification, and must work with the designer's rtl. Only simple tests may be written in such a way - initial checks of compilation, elaboration and non-algorithmic runtime errors.

The tested module must be instantiated into the top level testbench module. Usually, this instance is called DUT (or dut) - Design Under Test. The testbench's module doesn't have to have any ports so it's declaration is something like module tb;

The example of a one of simplest testbenches:

module tb();

reg clk = 1'b0;
always #10 clk = ~clk;

reg signed [7:0] a = -128, b = -128;
wire signed [8:0] c;

always @(posedge clk) begin
a <= a + 1;
if (a == 127) b <= b + 1;
end

subtractor dut (a, b, c);

endmodule

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