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What is an always block in Verilog, what is it used for, and how do I code it?

2 Answers

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An "always" block is one of the types of "procedural" blocks Verilog has. It allows for sequential execution of the statements inside the block. It's most often used for describing synchronous logic such as registers.

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This is a structural procedure that repeats continuously throughout the duration of the simulation. To be defined properly it must contain either a sensitivity list or a timing delay control.

Always blocks are used to specify both sequential logic and nodes of combinational logic. It can drive only variables (reg, integer etc data types). The sensitivity list is the one which defines events on which objects enable an execution of that always-block. This list is defined by the @ symbol after reserved word ' always' and the condition in parenthesis at where the block will be triggered.

Syntax:
always_construct ::= always statement

Examples:

  always @(posedge clk) begin
for (i = 0; i <= 63; i = i + 1) begin
if (i == addr_reg[5:0]) wl_o[i] = 1'b1;
else wl_o[i] = 1'b0;
end
end

always #10 clk = ~clk; // actually this is an ititial delay, but it is valid to use it for clock generation in testbenches.

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