Verilog Display?

Question

What is $display in Verilog and how do I use it?

Answer 1

In Verilog - "display" is a statement that's used for printing messages onto a console of a simulator. It's somewhat similar to "printf" in C.

"display" must be used inside an "always" or "initial" block.

Example :

initial
$ display ( " Hello World ! " ) ;

Answer 2

The $display system command displays a text on the screen during simulation every time it is executed and exactly when it is executed (not at the end of the current delta time-step how $strobe does). $display supports a C-like formatting.

$display(
  "\texpected dali data = %2h, received dali data = %2h",
    reftmp,
    rectmp
);

I use it to output a log, information messages, or check results for either debugging or information purposes.