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in Verilog by (200 points)

What is a Verilog module and how do you instantiate it?

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by (260 points)

A module is the basic design unit in Verilog. It describes the interfaces as well as the logic functionality of a logic block. The recommended way to instantiate a Verilog module is by using named ports.

Example :

module top
input wire clock ,
input wire [ 7:0 ] input_1 ,
input wire [ 7:0 ] input_2 ,
output wire [ 7:0 ] data_tx

some_component connect_some_component_to_top
.clk ( clock ) ,
.data_rx_1 ( input_1 ) ,
.data_rx_2 ( input_2 ) ,
.data_tx ( data_tx )
) ;

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by (260 points)

A Verilog module is a piece of HDL code that specifies either some hardware's or verification's behavior and can be used and reused within a project. In a sense, modules are rough equivalents of functions in other programming languages.

Verilog modules are base objects of a design hierarchical structure. Higher level modules create instances of lower level modules and communicate with them through input, output, and bidirectional ports.

A Verilog module Instantiation is the way to allow one module to include a copy of another module. This is an instrument of constructing a design's modules hierarchy. It creates one or more named instances of a defined module.

Also a module instantiation can contain a range specification. This allows you to create an array of module instances. Also recursive instances are possible, but some tools don't support this so you need to be carefull with it.

The syntax description of a module declaration and module instantiation are verbose but I beleive that it must be here because this is an important part of what a Verilog module is and how to instantiate it.

From the Verilog standard:

"A module definition shall be enclosed between the keywords module and endmodule. The identifier following the keyword module shall be the name of the module being defined. The optional list of parameter definitions shall specify an ordered list of the parameters for the module. The optional list of ports or port declarations shall specify an ordered list of the ports for the module. The order used in defining the list of parameters in the module_parameter_port_list and in the list of ports can be significant when instantiating the module. The identifiers in this list shall be declared in input, output, and inout statements within the module definition. Ports declared in the list of port declarations shall not be redeclared within the body of the module. The module items define what constitutes a module, and they include many different types of declarations and definitions, many of which have already been introduced."

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