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in Verilog by (240 points)

How do you create a Verilog array and how do you use it?

2 Answers

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by (300 points)

A creation of an array in Verilog is quite straight forward and can be done in a single line of code.

Example :

reg [ 7 : 0 ] d [ 2 : 0 ] ; // an array of 3 registers named 'd' - with each element being 8 bits long.
reg [ 7 : 0 ] q [ 2 : 0 ] ; // an array of 3 registers named 'q' - with each element being 8 bits long.

always @( posedge clock )
q [ 0 ] <= d [ 0 ] ;
q [ 1 ] <= d [ 1 ] ;
q [ 3 ] <= d [ 3 ] ;
0 votes
by (260 points)

In Verilog terms, not SystemVerilog (where there are packed and unpacked arrays):
An array is a collection of variables of the same type which are accessed using the same name and one or more indices. There are two kind of arrays:

1. A dimension declared before the array object name - so called 'vectors' and its dimension is referred to as the 'vector width'. It may have 1 or more dimensions.

reg [7:0] byte;
wire [3:0] [7:0] byte_word_net;
This kind of array is used to declare multiple bits wide data values. Only reg and wire objects can be of the vector type. Vectors can be assigned as a single unit.

2. Dimensions declared after the array object name - 'arrays' or memory in sometime cases. Usually this kind of array is used to declare a memory. But it also used to declare arrays of either vectors or scalar objects which need to have separate access (only single element by index, not a range of elements). It could also be used for a crossbar interface's buses or even an integer constants array.
reg [31:0] memory [0:255];
wire [DATA_WIDTH-1:0] buses [0:N-1];
integer initial_state_constants [0:3];
Arrays can't be assigned as a single unit. Only by a single index. Verilog vectors and arrays are indexed from left-bound to right-bound.
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