If Else If Verilog?

Question

How do you use an if, elseif, or else statement in Verilog?

Answer 1

Example :

wire [1:0] some_output ;
wire input_0 , input_1 ;

always @ *
begin

  if ( input_0 == input_1 )
    some_output = 2'b00 ;
  else
    some_output = 2'b01 ;
end

Answer 2

The Verilog if-statement is the same if-statement as in other languages - it is a conditional choice of statements to execute:

conditional_statement ::=
if ( expression )
statement_or_null [ else statement_or_null ]
| if_else_if_statement

if_else_if_statement ::=
if ( expression ) statement_or_null
{ else if ( expression ) statement_or_null }
[ else statement_or_null ]

statement ::=
{ attribute_instance } blocking_assignment ;
| { attribute_instance } case_statement
| { attribute_instance } conditional_statement
| { attribute_instance } disable_statement
| { attribute_instance } event_trigger
| { attribute_instance } loop_statement
| { attribute_instance } nonblocking_assignment ;
| { attribute_instance } par_block
| { attribute_instance } procedural_continuous_assignments ;
| { attribute_instance } procedural_timing_control_statement
| { attribute_instance } seq_block
| { attribute_instance } system_task_enable
| { attribute_instance } task_enable
| { attribute_instance } wait_statement
statement_or_null ::=
statement