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0 votes
in Verilog by (240 points)

How do you use a Verilog or gate?

2 Answers

0 votes
by (300 points)

An or gate is a basic logic circuit with the following "truth table" ( input-output relationship ) :

// when a = 0 and b = 0 - result = 0
// when a = 0 and b = 1 - result = 1
// when a = 1 and b = 0 - result = 1
// when a = 1 and b = 1 - result = 1

Example :

wire a , b , result;

assign result = a | b;
0 votes
by (260 points)

This is a built in primitive that implements the logic OR function.

or or1(out1,in1,in2,in3);
or or2(out2,in1,in2);
or or3(out3,in1);

// type:
`timescale 1ns/10ps
`celldefine
module OO1HSP (Z, A1, A2, B1, B2);
output Z;
input A1, A2, B1, B2;

// Function
or (Z, A1, A2, B1, B2);

// Timing
specify
(A1 => Z) = 0;
(A2 => Z) = 0;
(B1 => Z) = 0;
(B2 => Z) = 0;
endspecify
endmodule
`endcelldefine

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