Verilog OR?

Question

How do you use a Verilog or gate?

Answer 1

An or gate is a basic logic circuit with the following "truth table" ( input-output relationship ) :

// when a = 0 and b = 0 - result = 0
// when a = 0 and b = 1 - result = 1
// when a = 1 and b = 0 - result = 1
// when a = 1 and b = 1 - result = 1

Example :

wire a , b , result;

assign result = a | b;

Answer 2

This is a built in primitive that implements the logic OR function.

or or1(out1,in1,in2,in3);
or or2(out2,in1,in2);
or or3(out3,in1);

// type:  
`timescale 1ns/10ps
`celldefine
module OO1HSP (Z, A1, A2, B1, B2);
  output Z;
  input A1, A2, B1, B2;

  // Function
  or (Z, A1, A2, B1, B2);

  // Timing
  specify
    (A1 => Z) = 0;
    (A2 => Z) = 0;
    (B1 => Z) = 0;
    (B2 => Z) = 0;
  endspecify
endmodule
`endcelldefine