Assign Verilog?

Question

What does the assign statement do in Verilog and how do you use it?

Answer 1

Also known as "continuous assignment statement" - the "assign" statement is used for data-flow logic description. It's intended for modeling of combinatorial ( non sequential - such as a register ) logic.

Example 1 :

wire a;

assign a = 1'b1; // drive 'a' with a constant logic '1'.

Example 1 :

wire a;
wire c;

assign a = 1'b1; // drive 'a' with a constant logic '1'.
assign c = ~ a; // drive 'c' with the flipped value of 'a'.

Answer 2

This is a Continuous Assignment statement. Continuous assignments are used for combinational logic. It drives values into nets. The closest analogy is the wire.

This is also something like the concurrent signal assignment statement in VHDL. This assignment is activated by any changes on the right side. In that moment the right side is solved and the left side changes event with this right side result value is placed into the time loop to solve the left side object's value in the defined moment of the model time (either on the next delta-cycle or after the delay time).

Sytax:
assign [ strength ] [ #( delay ) ] net_name = expression;

Examples:

  assign xmdata_i = &mod_mode_i[1:0] ? xm_tx_data_i : 1'b0;
  assign txdata_i = !(&mod_mode_i[1:0]) ? xm_tx_data_i : 1'b0;
  assign xmsync_txclk_o = &mod_mode_i[1:0] ? xmsync_o : txclk_o;
  assign preamble_z_flag = &(preamble_container ^ ~(PREAMBLE_Z));
  assign #1 data_o = data_r;