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0 votes
in Verilog by (200 points)

How do you implement a counter in Verilog?

2 Answers

0 votes
by (220 points)

A counter in Verilog is a combination of an adder and a register.

Example :

reg [ 5:0 ] counter ;

always @ ( posedge clock )
begin
counter <= counter + 1 ;
end
0 votes
by (220 points)

reg [DATA_WITH-1:0] counter = {(DATA_WIDTH){1'b0}};
always @(posedge clk) begin
if (rst) counter <= {(DATA_WIDTH){1'b0}};
else counter <= counter + 1;
end

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