Verilog Counter?

Question

How do you implement a counter in Verilog?

Answer 1

A counter in Verilog is a combination of an adder and a register.

Example :

reg [ 5:0 ] counter ;

always @ ( posedge clock )
begin
  counter <= counter + 1 ;
end

Answer 2

reg [DATA_WITH-1:0] counter = {(DATA_WIDTH){1'b0}};
always @(posedge clk) begin
  if (rst) counter <= {(DATA_WIDTH){1'b0}};
  else counter <= counter + 1;
end