Clock Divider Verilog?

Question

How do I implement a clock divider in Verilog?

Answer 1

The core idea of a clock divider implementation is the same as with using VHDL. This is an implementation principle. The difference is only in coding.

The best way is to use PLLs or MMCM (Xilinx) if possible. You must place it's instances in your rtl.

There are other less recommended ways. Basicaly it is simple. But there are some details. Especially in ASIC design. When You code a clock divider you actually define (or derive) a new clock. This new clock needs to be constrained using sdc, fdc, lpf, or ucf. To do this well it would be better if this divider will be a dedicated entity for you to be able to target to its instance in a timing constraints file.

There are several variants to divide a clock. The best case is when you need to divide a clock by an even number. In such a case you can place an inverter at the divider output. Moreover, if you need to divide a clock by power of 2 - you can implement a chain of inverters so that you wouldn't need to use any combinational logic to compare counter outputs and this way will be best: simple and stable design with no probability of glitches.

And the most generic way - is a counter. Usually, I design it with a down count:

always @(posedge clk_p) begin
  reload <= 1'b0;
  if (b_cnt == 1)
    reload <= 1'b1;
  if (reload) 
    b_cnt <= b_reg;
  else
    b_cnt <= b_cnt - 1;
  if (!nclr_i)
    b_cnt <= 0;
end

assign clk_out = reload;

Answer 2

A clock divider takes an input frequency and the output frequency is equal to the input frequency divided by some integer. The code given below implements a clock divider on an FPGA:

module Clk_divider(clock_in,clock_out);
input clk_in; 
output clk_out; 
reg[27:0] counter=28'd0;
parameter DIVISOR = 28'd2;

always @(posedge clk_in)
begin
 counter <= counter + 28'd1;
 if(counter>=(DIVISOR-1))
  counter <= 28'd0;
end
assign clk_out = (counter<DIVISOR/2)?1'b0:1'b1;
endmodule