Verilog Shift Operator?

Question

What is a Verilog shift operator and how do you shift left and shift right?

Answer 1

<< - shift left
>> - shift right
<<< - arithmetic shift left (the same as << but I think it must to be a preserve of sign bit)
>>> - arithmetic shift right (with filling by a sign bit)

  reg [7:0] x = 8'b10101101;
  reg signed [7:0] x_signed;
  reg [7:0] x_unsigned;
  initial begin
    x_signed = x << 3; //01101000
    x_unsigned = x << 3; //01101000
    #10;
    x_signed = $signed(x) <<< 3; //01101000
    x_unsigned = x <<< 3; //01101000
    #10;
    x_signed = x >> 3; //00010101
    x_unsigned = x >> 3; //00010101
    #10;
    x_signed = $signed(x) >>> 3; //11110101
    x_unsigned = x >>> 3; //00010101
  end

Answer 2

Shift operators can be used to perform data shifts in a variable. Shift is performed on the left operand and the number of positions by which the data is shifted is given by the right operand. Both left and right shifts can be performed. A shift register can be quickly created by the shift operator. Shift operators are given as follows:

'<< ' (it performs logical left shift)
'>>' (it performs logical right shift)
'<<<' (it performs arithmatic left shift and sign is preserved)
'>>>' (it performs arithmatic right shift and the sign is preserved)

An example is given below:

reg [3:0] c;
c = 4'b1111;
c << 3 = 4'b1000
c >> 3 = 4'b0001
c << 1'bz = 4'bxxxx
c >> 1'bx = 4'bxxxx