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0 votes
in Verilog by (240 points)

How do you code a NOT in Verilog?

2 Answers

0 votes
by (200 points)

There are 2 kinds of 'not' in Verilog. The bit-wise combinational logic 'not' that is ~ (actually is an inversion) and the boolean 'not' that is the !-operator. The first one is an inversion, so it just inverts either the scalar single bit value or all the bits in a vector value. The second one checks the boolean expression: is it true or false. There is not any difference if it is applied to a scalar single bit value. But with vectors there is a difference.

Let reg [7:0] v; so '(~v & mask)' is mask 'and' the inversion of v, but (!v & mask) is the mask 'and' the scalar single bit result of if (v == 0).

Therefore I use ~ for combinational logic and ! - for boolean expressions (in if-statements or in the conditional expression of a conditional operator '?' for example).

0 votes
by (220 points)

Not gate code is pretty simple. Example of a gate level code is given below:

module not_gate(y,x);

input x;
output y;
not (y,x);
endmodule
Another way to code a NOT is:
module not_data(y,x);
input x;
output y;
assign y=~x;
endmodule

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