Parameter Verilog?

Question

What are parameters in Verilog and how do I use them?

Answer 1

Parameters are module constants that are available for configuration at compile time. Parameters allow customization of module instances. A parameter can be modified with the defparam statement or in the module instance statement.

Typically used to configure bus width, buffer depth, module's architecture configurations, latencies etc.

Syntax from the Verilog Standard:

parameter_declaration ::=
parameter [ signed ] [ range ] list_of_param_assignments
| parameter parameter_type list_of_param_assignments
parameter_type ::= integer | real | realtime | time
list_of_param_assignments ::= param_assignment { , param_assignment }
param_assignment ::= parameter_identifier = constant_mintypmax_expression
range ::= [ msb_constant_expression : lsb_constant_expression ]

Example:

module audio_extractor #(
  parameter CHANNEL_NUM = 8,
  parameter SYMBOL_WIDTH = 24) 
  (
  input clk_i
  input nrst_i
  input clr_i);

Answer 2

Parameters are of two types: module and specify. Module Parameters are constant values defined locally in a module. A set of attributes for a particular module can be defined with these parameters and these attributes determine the modules behaviour and physical representations. They can be overridden at the time of instantiation. 'defparam' can also be used for overriding. A hierarchal pathway to the parameter must be defined. A simple way to define a parameter is to use the keyword 'parameter':

parameter data_x = 8 ;

To further explain, Syntax is given as:

parameter identifier = constant_expression ,
defparam hierarchical_path = constant_expression ;

Parameters can also be declared inside the specify block and they are mainly used to provide timing and delay values. These parameters can also be declared inside the main module. They are declared using the specparam key word. An example is:

 specify
    specparam  t_rise = 200, t_fall = 150;
    specparam  clk_to_q = 70, d_to_q = 100;
  endspecify