Verilog While Loop?

Question

How do you do a while loop in Verilog?

Answer 1

From the Verilog standard: while ( expression ) statement
The while loop executes statement until an expression becomes false. If the expression starts out false the statement shall not be executed.

Usually I use this loop scheme in tests - to define some waiting or transmitting behavior. Or in computations that decides parameters values.

  while (!(dali_done === 1'b0)) @(posedge isys_clk);

  task form_reference_data(logic[`DATA_WIDTH-1:0] val); 
  begin
    @(posedge aes3_to_i2s_test_info.clk_sync);
    aes3_to_i2s_test_info.tx_init = 1;
    aes3_to_i2s_test_info.data_expected = val;
    id++;
    while (aes3_to_i2s_test_info.tx_init) begin
      @(posedge aes3_to_i2s_test_info.clk_sync);
      if (aes3_to_i2s_test_info.tx_init_acknowledged)
          aes3_to_i2s_test_info.tx_init = 0;
    end
  end
  endtask : form_reference_data

Answer 2

While loop is used when we need to repeat run some particular code until some condition is true. While loop is not used for synthesizable code because the exact number of iterations is not known. Syntax of the while loop is explained by the example code below:

initial 
begin 
  i = 0; 
  while( i <= 20 ) 
  begin 
     #2 $display("i= ", i); 
     i = i + 1; 
  end 
end

The 2 lines inside the while loop will run over and over again until i is less than or equal to 20. Initial value of i is set at 0. With each iteration the value of i is incremented by one.