Concatenation in Verilog?

Question

How do you do concatenation in Verilog?

Answer 1

"A concatenation is the result of the joining together of bits resulting from one or more expressions. The concatenation shall be expressed using the brace characters { and }, with commas separating the expressions within.

Unsized constant numbers shall not be allowed in concatenations. This is because the size of each operand in the concatenation is needed to calculate the complete size of the concatenation.

An operator that can be applied only to concatenations is replication, which is expressed by a concatenation preceded by a non-negative, non-x and non-z constant expression, called a replication constant, enclosed together within brace characters, and which indicates a joining together of that many copies of the concatenation. Unlike regular concatenations, expressions containing replications shall not appear on the left-hand side of an assignment and shall not be connected to output or inout ports."

Examples:

reg [7:0] data_h, data_l;
reg [2:0] field0;
reg [12:0] field1;

always @(posedge clk) begin
    {field0, field1} <= {data_h, data_l};
end

Answer 2

In verilog, concatenation combines two or more types together. The curly brackets {,} are used for this operation. The expressions you want to concatenate are written inside the curly brackets and separated by a comma. The syntax is:

{expression_1, expression_2}

Another way of doing concatenation is:

{multiplier{expression}}

This is used when you want to duplicate 'expression' a number of times as the constant 'multiplier'.