Verilog vs SystemVerilog?

Question

What is the difference between Verilog and SystemVerilog?

Answer 1

SystemVerilog has grown from the verification extension of the Verilog standard. This is much more powerful language than Verilog. SystemVerilog main features are:
- user defined types such as structures and enumerations
- packed and unpacked arrays and structures
- always_comb, always_latch, always_ff that have a strictly defined application. Software tools must throw a warning if the code in such blocks doesn't implement needed behavior
- logic type instead reg and wire
- $clog2 function. This simple function is very very useful.
- interfaces
- packages
- powerful verification subset with: classes, DPI (I believe that this is mostly a verification feature), randomization, process flow control, assertions, and all this is enhanced by UVM and SVA.

Answer 2

System Verilog is a hardware description language as well as a hardware verification language. Verilog is simply a hardware description language. System Verilog is an advanced version of Verilog. It is used for more complex design and verification. System Verilog is an object-oriented language and contains more features than Verilog, it has numerous data types as opposed to Verilog that has only two main data types: reg and wire. System Verilog is based on classes that are dynamic in nature while Verilog is based on modules, thus class level test bench is used by system Verilog and module level test bench is used by Verilog.