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in Verilog by (200 points)

What is 'delay' in Verilog and how is it used?

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Propagation of values through nets or gates is specified by delay. The time needed to move values from drivers through the net is specified by the net delay. The time it takes for a signal change to propagate from input to output of a gate is specified by gate delay declaration. Procedural control statement sometimes also need a delay. The syntax given below further explains the concept of delay in Verilog:

assign #5 out = in1 & in2;

This snippet of code means that gate delay value is 5 time units. So, changes in inputs (in1 and in2) will propagate to output in 5 time units. Another example using multiple delay declaration is given as under:

assign #(5,3,7) w_or = |bus;

The value of the delay used depends on the value of the right-hand side of the expression. If the right-hand side is evaluated to be 1 then delay will be 5 time units but if the right-hand side is evaluated to be zero then the delay will be 3 units. If the right-hand side has high impedance then the delay value of 7 is used. If the right-hand side expression returns an unknown value then the smallest delay (3 time units) will be used.

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1. There is delay which specified in a net declaration (wire #6 a;) This is a net delay. It means that any value change that is to be applied to wire a by some other statement shall be delayed for 6 time units before it takes effect. This is about a transport delay.

2. Continuous assignment delay. This delay is to specify the time duration between a right-hand operand value change and the actual assignment to the left-hand side. This is about transport delay.

3. Procedural timing control delays. This delay control specifies an execution delay of the folowing statement. In combination with a non-blocking assignment it makes a transport delay:

always @(*) #5 d_delayes <= d;

4. Delays in the timing control of a procedural assignment. It may placed after '<=' or '='. This delay specifies the time duration between the right side change and both the right side evaluation and assignement execution.

always @(*) d_delayes = #5 d;

After 'd' has changed it waits the 5 time units, then evaluates d and executes the assignment. In combination with a blocking procedural assignment it makes the inertial delay.

Note for 3 and 4:
This is wrong to use #<delay> a_delayed = d; and a_delayed <= #<delay> a; When you need a transport delay you must use procedural timing control + non-blocking assignment; when you need an inertial delay - procedural assignment timing control + blocking assignment;

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