Shift Register Verilog?

Question

What is a shift register and how do I code it in Verilog?

Answer 1

In simple terms the shift register is a chain of flip-flops connected in series, so that the output of one flipflop feeds into the input of the next. It shifts the current state of this chain and the input of a first flipflop throughout all the chain at each clock edge.

Mostly I code it in a way like this:

  reg [D_WIDTH-1:0] shifterg = 0;
  always @(posedge clk) shiftreg <= {shiftreg[D_WIDTH-2:0], in};

or it might be:

  always @(posedge clk) begin
    shiftreg <= shiftreg << 1;
    shiftreg[0] <= in;
  end

Or it might be more interesting structure with value loading, with a shift value > 1, with another direction and so on. But the main principle is described above.

Answer 2

A shift register consists of multiple storage elements (flip-flops) connected in series. Shift registers are used for delays and for the conversion of data from serial to parallel or from parallel to serial. The shift register can be created by using the 'shift operator'.

reg [3:0] Input_Delay;
 always @(posedge clock)
  begin
    // delayed signal Input created
    Input_Delay    <= Input_Delay << 1;
    Input_Delay[0] <= Input;

    // it can also be done without shift operator
    Input_Delay[1] <= Input_Delay[0];
    Input_Delay[2] <= Input_Delay[1];
    Input_Delay[3] <= Input_Delay[2];
    Input_Delay[0] <= Input;

    if (Input_Delay[3] == 1'b1)
      // Do Stuff
  end